1. Field of the Invention
The present invention relates to a pulse generating system which responds to instruction pulses for generating driving pulses which drive a motor. The present invention is applicable to a circuit for driving and controlling the rotation of a stepper motor which is used in a magnetic-disk drive. In the magnetic-disk drive, the stepper motor moves a magnetic read/write head so as to position the head at a desired track of the magnetic disk.
2. Related Art
A step-pulse generating circuit acting as the pulse generating system in the related art used in the magnetic-disk drive controls the rotation of the stepper motor in the magnetic-disk drive. A series of external step pulses are input to the step-pulse generating circuit and using the series of external pulses, the step-pulse generating circuit generates a series of exciting step pulses. The term `step` of the step pulse may have been derived from the use of the stepper motor. Each of the step pulses is a pulse be used to cause the stepper motor to move the magnetic read/write head through a disk actuator arm from one track to the next. The series of exciting step pulses are used to control the rotation of the stepper motor. Using the series of exciting step pulses, a stepper motor control circuit generates series of exciting pulses for each phase of the stepper motor and the thus generated series of exciting pulses for each phase are supplied to respective phase terminals of the stepper motor.
The step-pulse generating circuit has therein a reference-clock generating circuit for generating a series of reference clock pulses. A time span of the above-mentioned series of exciting step pulses is defined using the series of reference clock pulses. The thus-defined time span of the series of exciting step pulses corresponds to an exciting time of the stepper motor. The exciting time of the stepper motor is a time during which an exciting pulse of the series of exciting pulses excites relevant windings of the stepper motor, thus moving the stepper motor as a result of interaction between relevant magnets and the windings in the stepper motor.
Some of such magnetic-disk drives have a power-saving mode for reducing power consumption. Such a magnetic-disk drive with the power-saving mode enters into the power-saving mode if no instructions have been input from outside of the magnetic-disk drive thereto for a predetermined time period. In the power-saving mode, the magnetic-disk drive stops operations of parts/components therein which are not necessary during a time during which no instructions are input from outside of the magnetic-disk drive thereto. Thus, power consumption is reduced. Specifically, if no instructions are input from outside of the magnetic-disk drive, no external step pulses have been input to the step-pulse generating circuit. As a result, in the power-saving mode, the step-pulse generating circuit in the magnetic-disk drive stops an operation of generating the series of exciting step pulses.
However, the above-mentioned reference-clock generating circuit is kept in a state in which the reference clock pulses are still generated in the power-saving mode. As a result, if input of the series of external step pulses to the step-pulse generating circuit in the power-saving mode, the step-pulse generating circuit is started can immediately respond to the input of the series of external step pulses so as to generate the series of exciting step pulses without substantial time delay.
However, the reference-clock generating circuit consumes a relatively large amount of power for a pulse oscillation operation. Therefore, it is preferable to also stop the operation of the reference-clock generating circuit in the power-saving mode in order to improve the power saving effect.
With reference to FIG. 1A, a crystal oscillation circuit will be described. The crystal oscillation circuit consists of a quartz crystal resonator 56, an inverter circuit 57, a resistor R.sub.53, and capacitors C.sub.54, C.sub.55. A series of pulses obtained by an oscillation operation performed by the oscillation circuit can be obtained from a point at which the inverter circuit 57, resistor R.sub.53 and quartz crystal resonator 56 are connected with one another. Another inverter circuit 52 is connected between the above connecting point and an output terminal 72. Such a circuit construction has been well-known as a typical crystal oscillation circuit. Such a crystal oscillation circuit may be used as the above-mentioned reference-clock generating circuit in the related art. The reference-clock generating circuit is used in a condition in which stopping of the pulse oscillation (generating) operation is not necessary.
With reference to FIG. 1B, a type of the reference-clock generating circuit will be described. This type of the reference-clock generating circuit is obtained as a result of modifying the above-mentioned reference-clock generating circuit in the related art. In this type of the reference-clock generating circuit, the pulse generation operation can be stopped in the power-saving mode. In the reference-clock generating circuit shown in FIG. 1B, a NAND circuit 51 is used instead of the inverter circuit 57 used in the circuit shown in FIG. 1A. By the oscillation function of the crystal oscillation circuit using the quartz crystal resonator 56, the reference-clock generating circuit shown in FIG. 1 outputs the series of reference clock pulses via the output terminal 72.
In the power-saving mode, a signal is input to the reference-clock generating circuit at a control terminal 71 so that a level of the control terminal 71 becomes a low level. As a result, the oscillation operation in the circuit is stopped. If the relevant step-pulse generating circuit goes out of the power-saving mode, a signal is input to the reference-clock generating circuit at the control terminal 71 so that the level of the control terminal 71 is changed from the low level to a high level. As a result, the oscillation operation is started in the reference-clock generating circuit.
The reference-clock generating circuit shown in FIG. 1 has a starting time since the circuit has been started, which time is the time required for the oscillation state thereof to reach a steady state. If supply of the above-mentioned series of external step pulses is started in the power-saving mode, the reference-clock generating circuit then starts to generate the series of reference clock pulses. The relevant step-pulse generating circuit thus uses the thus-generated reference clock pulses so as to generate the above-mentioned series of exciting step pulses. Such a starting time as mentioned above may prevent the series of exciting step pulses from being obtained in a timely manner if a time span between each two adjacent pulses of the series of external step pulses is too short. In such a case, the rotation of the stepper motor may not be properly controlled through the step-pulse generating circuit.